Electrostatic discharge (ESD), which is the rapid discharge of static electricity from one conductive material to another, can damage computer equipment. An electric charge transfers from one conductor to another because of a difference in electrical potential of the conductive bodies. As used herein, an ESD event is the occurrence of an electrostatic discharge.
ESD can negatively affect computer equipment in many ways. An ESD event during manufacturing can cause product defects. An ESD event during operation can cause a product to malfunction or incur temporary or permanent damage. To prevent or control ESD events during operation, conventional computer equipment often includes ESD circuitry to route discharged static electricity away from critical components (e.g. to a ground reference). In general, ESD circuitry may be implemented to protect integrated circuits and microchips. In a particular example, ESD circuitry may be used to protect a random access memory (RAM) device.
FIG. 1 depicts a conventional ESD circuit. The conventional ESD circuit includes a trigger circuit and an ESD shunt circuit. The trigger circuit controls the operation of the ESD shunt circuit. When the trigger circuit detects an ESD current on the power source, vpwr2, (which is also present on the power source, vpwr1), the trigger circuit sends a control signal, trig, to the ESD shunt circuit. The ESD shunt circuit includes a high voltage (HV) transistor. When the ESD shunt circuit is turned on by the trigger circuit, the ESD shunt circuit provides an electrical path between the power source, vpwr1, and the ground reference, vgnd, so that the ESD voltage and current are conducted to the ground reference. In this way, electrical components connected to the power source, vpwr1, are protected from damage due to the ESD event. The high voltage transistor is protected against damage during the ESD event because it has a relatively thick gate oxide layer. An exemplary thickness of a thick gate oxide layer of a high voltage transistor is approximately 60 Å (60×10−10 m).
During normal operation, before and after an ESD event, the control signal is driven low (e.g., to vgnd) so that the high voltage transistor is turned off. Turning off the high voltage transistor prevents unintended current flow from the voltage source to the ground reference during normal operation. In order for the low control signal to turn off the high voltage transistor, the high voltage transistor must have a positive threshold voltage. However, many modern technologies use native transistors that are not doped to raise the threshold voltage. In fact, some modern technologies use threshold voltages that are zero or slightly negative for cost savings in manufacturing. In addition to increasing the mask and manufacturing cost, the high voltage transistors yield lower drive current per unit width of the transistor compared to a low voltage transistor under the same bias conditions.
Currently, high voltage transistors with a positive threshold voltage are not used as frequently in many newly developed products and technologies. Additionally, new technologies often incorporate low voltage (LV) transistors in order to reduce power requirements or obtain other benefits. However, the use of low voltage transistors can present a challenge in designing ESD circuits because low voltage transistors do not sustain ESD voltages to the same degree as high voltage transistors. For example, a low voltage transistor may be designed for normal operation at approximately 1.8 volts, but a high voltage transistor may be designed for normal operation at greater than 1.8 volts. The relative operating voltages of low and high voltage transistors is related to the relative gate oxide thickness of low and high voltage transistors—transistors with thicker gate oxide layers can operate at high voltages. An exemplary thickness of a gate oxide layer of a low voltage transistor is approximately 20 Å (20×10−10 m).
Thus, where a single high voltage transistor is used to provide ESD protection in an ESD circuit, the ESD shunt circuit may be incompatible with a modern technology that uses low voltage (LV) transistors and/or lower threshold voltage transistors. Additionally, the protective functionality of the ESD shunt circuit is limited by the gate oxide stress voltage of the single high voltage transistor. Addition of a high voltage transistor with non-zero, positive threshold voltage to the process increases the mask and manufacturing cost. For high volume, low cost products this is not an economically viable solution.